1. Field of the Invention
This invention relates to clock systems employed to time the operation of processors and input-output units associated with cache memories. More particularly, this invention relates to a synchronizing clock system for providing a fail soft clock.
2. Discussion of the Prior Art
Most central processing units are provided with a source of central clock pulses which are employed to time the operation of the processing unit. Processing systems employing a limited number of input-output units and some external memory have employed the central clock pulses of the central processing unit to time the operation of the equipment outside of the central processing unit main cabinet. The timing of a system having a single central processing unit does not present a problem of synchronization because the system can be timed from a single master clock. If provisions for a fail soft clock system are required, a standby or back-up clock can be provided. The back-up clock can be synchronized with the active clock by phase lock loops or other known techniques.
Large data processing systems employ two or more central processing units, each having their own source of master clock pulses. Usually the master clock pulses are of a duration much shorter than the cycle and response times of the active components of the system or of the central processing units and the associated cache memories and/or the input-output units.
Several problems are presented when the master clock pulses of more than one central processing unit are present in a large data processing system. First, the clock pulses are usually of frequencies in excess of twenty megahertz, thus, individual pulse durations are less than twenty-five nanoseconds duration. The cables employed to connect the components of the system may be as long as twelve feet, thus, the time delay in the coaxial cables will exceed eighteen nanoseconds in each direction. It would not be possible to issue a request and receive acknowledgement between components of a large data processing system in the time duration of a single master clock timing pulse, accordingly, it is necessary to provide internal counters and associated circuits to generate cycle times within the individual components of the system. Since the cycle times of the individual components are synchronized by timing pulses from a remotely located master clock, the timing pulses will arrive after being delayed in the connecting cables.
Heretofore, delays of pulses were compensated for by placing additional compensating delay devices in the connecting cables so that similar master clock pulses arrived at all components in the system simultaneously. When more than one clock is to be employed in a large data processing system, the paths taken by the different master clock pulses will be different and the compensating delays would require being changed each time a different clock is to be employed.
Large data processing systems require alternative clocks as a safety precaution for at least two reasons. To make a large data processing system fail soft, there must always be a master clock system and a back-up clock system. These clocks must be synchronized. Clocks that are timed together in phase lock loops are not independent of each other and do not meet the general requirements of a fail soft system.
Another important reason for providing alternative master clocks in a large central processing system is that each system usually employs volatile solid state memory devices in a volatile cache memory. Volatile solid state cache memory devices are desirable because they can be made to operate much faster than non-volatile type solid state memory devices. Volatile solid state memory devices lose or drop their stored data within a very short period of time if refresh address signals are not applied to the memory devices. It has become a preferred practice to time the refresh address signals of a cache memory with the master clock pulses of the data processing system to avoid interference with data being processed.
Yet another problem is presented in the use of very fast solid state memory devices for volatile solid state memories. When the solid state memory is ready to accept a request for the input or output of data it produces a signal equivalent to a ready signal at its interface internal gating circuits. When a stabilized request is present at the input of the solid state memory when the ready signal is first presented, the request is properly accepted and executed. A request which occurs while the ready signal is still stable is also properly accepted and executed, however, when the ready signal is terminated and the request signal is in a period of transition, the interface receiving circuit can propagate the transitional instability leaving the state of the receiver and the memory uncertain.
The problem with volatile solid state memory devices employing transistor-transistor-logic (TTL) and emitter-coupled-logic (ECL) at the receiving interface is that when the request is not stable when the ready signal terminates there is a period of instability referred to as metastability. For example, a commercially-available ECL flip-flop is specified to require data input stable a minimum of 0.1 nanosecond before and after the presentation of the enable or clock input to guarantee that a stable latch or change of state condition will be performed.
It is a requirement for large scale data processing systems to provide requests from all components which generate requests for a period in excess of that specified by semi-conductor manufacturers. It is impossible to meet this requirement without timing the output of the sending unit with the same master clock which times the ready signal of the cache memory interface receiver. This cannot be accomplished presenting synchronized timing pulses to the input of all the components in a large scale data processing system.
When the above problem of metastability is presented in a fail soft system and in a system where two or more master clocks are interchangeably employed, the problem is more complex.